In May 8, 2012, promote the use of TSV ( TSV ) 3D laminated to a
In May 8, 2012, promote the use of TSV ( TSV ) 3D laminated to a new generation of DRAM " Hybrid Memory Cube ( HMC ) Hybrid Memory Cube Consortium " popularity ( HMCC ) announced that the United States, software giant Microsoft has joined the association.
HMC is the three-dimensional structure, the logic chip along the vertical direction superposition of multiple DRAM chips, and then through the TSV connection wiring technology. HMC 's biggest characteristic is compared with existing DRAM, performance can be greatly improved. The reasons there are two, one is between chips from semiconductor package wiring distance on a board on the traditional methods of " cm " units are substantially reduced to dozens ofμ m～ 1mm; two is on a chip to form 1000 to tens of thousands of TSV, realize the multipoint connection chip.
Microsoft 's accession to the HMCC, because we are considering how to corresponding is likely to become a personal computer and a computer to improving the performance of " memory bottleneck " problem. Memory bottleneck refers to as the microprocessor performance through multiple nucleation and constantly improve, the architecture of the DRAM performance will not be able to meet the need of processor. If do not solve this problem, can occur even if the computer new product, the actual performance is also not appropriate promotion situation. Compared with it, if the TSV based on the application of HMC in computer main memory, the data transmission speed can be increased to the current DRAM is about 15 times, therefore, is not just a giant Microsoft, American companies such as Intel are also active in research using HMC.
In fact, plans to use TSV not only for HMC and other DRAM products. According to the semiconductor manufacturers plan, in the next few years, borne from electronic equipment input function of the CMOS sensor to the responsible for the operations of FPGA and multi core processor, and in charge of product storage of DRAM and NAND flash will have to import TSV. If the plan goes ahead, TSV will assume the input, operation, storage and other electronic equipment main function.
In May 8, 2012, promote the use of TSV ( TSV ) 3D laminated to a new generation of DRAM " Hybrid Memory Cube ( HMC ) Hybrid Memory Cube Consortium " popularity ( HMCC ) announced that the United States, software giant Microsoft has joined the association.
HMC is the three-dimensional structure, the logic chip along the vertical direction superposition of multiple DRAM chips, and then through the TSV connection wiring technology. HMC 's biggest characteristic is compared with existing DRAM, performance can be greatly improved. The reasons there are two, one is between chips from semiconductor package wiring distance on a board on the traditional methods of " cm " units are substantially reduced to dozens ofμ m～ 1mm; two is on a chip to form 1000 to tens of thousands of TSV, realize the multipoint connection chip.
Microsoft 's accession to the HMCC, because we are considering how to corresponding is likely to become a personal computer and a computer to improving the performance of " memory bottleneck " problem. Memory bottleneck refers to as the microprocessor performance through multiple nucleation and constantly improve, the architecture of the DRAM performance will not be able to meet the need of processor. If do not solve this problem, can occur even if the computer new product, the actual performance is also not appropriate promotion situation. Compared with it, if the TSV based on the application of HMC in computer main memory, the data transmission speed can be increased to the current DRAM is about 15 times, therefore, is not just a giant Microsoft, American companies such as Intel are also active in research using HMC.
In fact, plans to use TSV not only for HMC and other DRAM products. According to the semiconductor manufacturers plan, in the next few years, borne from electronic equipment input function of the CMOS sensor to the responsible for the operations of FPGA and multi core processor, and in charge of product storage of DRAM and NAND flash will have to import TSV. If the plan goes ahead, TSV will assume the input, operation, storage and other electronic equipment main function.
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